1. Field of the Invention
The present invention relates to a method for hardening integrated circuits in general and MOS circuits in particular.
2. Prior Art
Elimination of failures or performance degradation of integrated circuits due to exposure to high energy radiation is an important goal for all space and military electronic systems.
One very important failure and degradation mechanism which is operative in VLSI MOSFET circuits is the development of radiation-induced interface states in the thin gate oxides which control MOSFET operation. The current state-of-the-art processing of VLSI MOS devices is based on fine control of the various wafer processing steps. This control consists of minimizing the water content in the oxide and not allowing temperatures to exceed 900.degree. C. at any time following the gate oxidation step. An example of this approach is the Sandia National Laboratory's 4/3 micron process. The process is described in more detail in Winokur, P. S.; Errett, E. B.; Fleetwood, D. M.; Dressendorfer, P. V.; and Turpin, D. C., in the 1985 IEEE Transactions of Nuclear Science, (NS-32), page 3954. Some of the key features of this process are a 1000.degree. C. dry oxidation, a 900.degree. C. post-gate anneal in forming gas, and a TEOS densification step. These parameters were determined from a long series of optimization studies of the Sandia device fabrication process and are relevant to the particular Sandia production facility. The optimal process sequence results in best case voltage shifts due to interface state generation of about 1.5 V at 1 Mrad(Si) total dose.
There are several shortcomings in the current state-of-the-art radiation hardening techniques. First of all, there is still significant interface state growth upon exposure to ionizing radiation in devices produced by these techniques. Second, the process restricts the use of common commercial IC processing steps, such as high temperature reflow anneals, which are used to increase device yield and performance. Third, these processes must be strictly controlled; a very small variation can result in a dramatic reduction in device radiation hardness. Thus, current radiation-hardened technology results in low yield and parts which suffer performance degradation due to interface state growth in an ionizing radiation environment.
Another method for improving the radiation hardness of silicon solar cells by implantation of lithium ions into the wafer is described in U.S. Pat. No. 4,608,452. The lithium ions are used to create electrically active defects. Those defects can then be annealed out at a lower temperature than radiation-induced defects. One shortcoming of this method is that the lithium ions create different defects and do not directly reduce the existing defects in the silicon.
It is therefore an object of this invention to improve radiation-hardening of MOS circuits by reducing the growth of interface states caused by ionizing radiation.
Another object of this invention is to permit the use of common commercial IC processing steps in the production of rad-hard MOS circuits.
Yet another object of this invention is to loosen the process restrictions for a rad-hard technology and to improve yield.
Another object of this invention is to provide a simple method of reducing the number of electrically active defects in the silicon dioxide.